Add base DTS file for PMH0101 including temp-alarm, GPIO,
PWM and flash nodes.

Link: https://lore.kernel.org/linux-arm-msm/[email protected]/
Signed-off-by: Jishnu Prakash <[email protected]>
Signed-off-by: Kamal Wadhwa <[email protected]>
Signed-off-by: Jingyi Wang <[email protected]>
Signed-off-by: Sibi Sankar <[email protected]>

Add base DTS file for PMH0104 inclduing temp-alarm and GPIO nodes.

Link: https://lore.kernel.org/linux-arm-msm/[email protected]/
Signed-off-by: Jishnu Prakash <[email protected]>
Signed-off-by: Kamal Wadhwa <[email protected]>
Signed-off-by: Jingyi Wang <[email protected]>
Signed-off-by: Sibi Sankar <[email protected]>

Add base DTS file for PMH0110 including temp-alarm and GPIO nodes.

Link: https://lore.kernel.org/linux-arm-msm/[email protected]/
Signed-off-by: Jishnu Prakash <[email protected]>
Signed-off-by: Kamal Wadhwa <[email protected]>
Signed-off-by: Jingyi Wang <[email protected]>
Signed-off-by: Sibi Sankar <[email protected]>

Document Glymur SoC bindings and Compute Reference Device
(CRD) board id

Link: https://lore.kernel.org/lkml/20250925-v3_glymur_introduction-v1-1-24b601bbecc0@oss.qualcomm.com/
Signed-off-by: Pankaj Patil <[email protected]>
Signed-off-by: Sibi Sankar <[email protected]>

Introduce initial device tree support for Glymur - Qualcomm's
next-generation compute SoC and it's associated Compute Reference
Device (CRD) platform.

The dt describes CPUs, CPU map, GCC and RPMHCC clock controllers,
geni UART, interrupt controller, TLMM, reserved memory,
interconnects, SMMU, firmware scm, watchdog, apps rsc, RPMHPD,
SRAM, PSCI and pmu nodes.

Link: https://lore.kernel.org/lkml/20250925-v3_glymur_introduction-v1-3-24b601bbecc0@oss.qualcomm.com/
Signed-off-by: Pankaj Patil <[email protected]>
Signed-off-by: Sibi Sankar <[email protected]>

…l engines

Add device tree support for QUPv3 serial engine protocols on Glymur.
Glymur has 24 QUP serial engines across 3 QUP wrappers, each with
support of GPI DMA engines.

Link: https://lore.kernel.org/lkml/20250925-v3_glymur_introduction-v1-4-24b601bbecc0@oss.qualcomm.com/
Signed-off-by: Jyothi Kumar Seerapu <[email protected]>
Signed-off-by: Pankaj Patil <[email protected]>
Signed-off-by: Sibi Sankar <[email protected]>

Add CPU power domains

Link: https://lore.kernel.org/lkml/20250925-v3_glymur_introduction-v1-5-24b601bbecc0@oss.qualcomm.com/
Signed-off-by: Maulik Shah <[email protected]>
Signed-off-by: Pankaj Patil <[email protected]>
Signed-off-by: Sibi Sankar <[email protected]>

Enable pdp0 mailbox node on Glymur SoCs.

Link: https://lore.kernel.org/lkml/20250925-v3_glymur_introduction-v1-6-24b601bbecc0@oss.qualcomm.com/
Signed-off-by: Pankaj Patil <[email protected]>
Signed-off-by: Sibi Sankar <[email protected]>

Add sram and scmi nodes required to have a functional cpu dvfs
on Glymur SoCs.

Link: https://lore.kernel.org/lkml/20250925-v3_glymur_introduction-v1-7-24b601bbecc0@oss.qualcomm.com/
Signed-off-by: Taniya Das <[email protected]>
Signed-off-by: Pankaj Patil <[email protected]>
Signed-off-by: Sibi Sankar <[email protected]>

Add RPMH regulator rails for Glymur CRD.

Link: https://lore.kernel.org/lkml/20250925-v3_glymur_introduction-v1-9-24b601bbecc0@oss.qualcomm.com/
Signed-off-by: Kamal Wadhwa <[email protected]>
Signed-off-by: Pankaj Patil <[email protected]>
Signed-off-by: Sibi Sankar <[email protected]>

Add spmi-pmic-arb device for the SPMI PMIC arbiter found on
Glymur. It has three subnodes corresponding to the SPMI0,
SPMI1 & SPMI2 bus controllers.

Link: https://lore.kernel.org/lkml/20250925-v3_glymur_introduction-v1-10-24b601bbecc0@oss.qualcomm.com/
Signed-off-by: Kamal Wadhwa <[email protected]>
Signed-off-by: Pankaj Patil <[email protected]>
Signed-off-by: Sibi Sankar <[email protected]>

Add base DTS file for PMCX0102 along with temp-alarm and GPIO
nodes.

Link: https://lore.kernel.org/lkml/20250925-v3_glymur_introduction-v1-11-24b601bbecc0@oss.qualcomm.com/
Signed-off-by: Kamal Wadhwa <[email protected]>
Signed-off-by: Pankaj Patil <[email protected]>
Signed-off-by: Sibi Sankar <[email protected]>

Update the pmh0104.dtsi to include multiple instances of PMH0104
DT nodes, one for each SID assigned to this PMIC on the spmi_bus0
and spmi_bus1 in Glymur CRD board.

Take care to avoid compilation issue with the existing nodes by
gaurding each PMH0104 nodes with `#ifdef` for its corresponding
SID macro. So that only the nodes which have the their SID macro
defined are the only ones picked for compilation.

Link: https://lore.kernel.org/lkml/20250925-v3_glymur_introduction-v1-13-24b601bbecc0@oss.qualcomm.com/
Signed-off-by: Kamal Wadhwa <[email protected]>
Signed-off-by: Pankaj Patil <[email protected]>
Signed-off-by: Sibi Sankar <[email protected]>

Add multiple instance of PMH0110 DT node, one for each assigned
SID for this PMIC on the spmi_bus0 and spmi_bus1 on the Glymur
CRD.

Take care to avoid compilation issue with the existing nodes by
gaurding each PMH0110 nodes with `#ifdef` for its corresponding
SID macro. So that only the nodes which have the their SID macro
defined are the only ones picked for compilation.

Link: https://lore.kernel.org/lkml/20250925-v3_glymur_introduction-v1-14-24b601bbecc0@oss.qualcomm.com/
Signed-off-by: Kamal Wadhwa <[email protected]>
Signed-off-by: Pankaj Patil <[email protected]>
Signed-off-by: Sibi Sankar <[email protected]>

Include all the PMICs present on the Glymur board into
the glymur CRD DTS file.

Link: https://lore.kernel.org/lkml/20250925-v3_glymur_introduction-v1-15-24b601bbecc0@oss.qualcomm.com/
Signed-off-by: Kamal Wadhwa <[email protected]>
Signed-off-by: Pankaj Patil <[email protected]>
Signed-off-by: Sibi Sankar <[email protected]>

Add Volume Down/Up keys for Glymur CRD.

Link: https://lore.kernel.org/lkml/20250925-v3_glymur_introduction-v1-16-24b601bbecc0@oss.qualcomm.com/
Signed-off-by: Kamal Wadhwa <[email protected]>
Signed-off-by: Pankaj Patil <[email protected]>
Signed-off-by: Sibi Sankar <[email protected]>

On Glymur boards, the RTC alarm interrupts are routed to SOCCP
subsystems and are not available to APPS. This can cause the
RTC probe failure as the RTC IRQ registration will fail in
probe.

Fix this issue by adding `no-alarm` property in the RTC DT
node. This will skip the RTC alarm irq registration and
the RTC probe will return success.

Link: https://lore.kernel.org/lkml/20250925-v3_glymur_introduction-v1-17-24b601bbecc0@oss.qualcomm.com/
Signed-off-by: Kamal Wadhwa <[email protected]>
Signed-off-by: Pankaj Patil <[email protected]>
Signed-off-by: Sibi Sankar <[email protected]>

Describe PCIe5 controller and PHY. Also add required system resources like
regulators, clocks, interrupts and registers configuration for PCIe5.

Link: https://lore.kernel.org/lkml/20250925-v3_glymur_introduction-v1-19-24b601bbecc0@oss.qualcomm.com/
Signed-off-by: Prudhvi Yarlagadda <[email protected]>
Signed-off-by: Qiang Yu <[email protected]>
Signed-off-by: Pankaj Patil <[email protected]>
Signed-off-by: Sibi Sankar <[email protected]>

… signal for pcie5

Add perst, wake and clkreq sideband signals and required regulators in
PCIe5 controller and PHY device tree node.

Link: https://lore.kernel.org/lkml/20250925-v3_glymur_introduction-v1-20-24b601bbecc0@oss.qualcomm.com/
Signed-off-by: Qiang Yu <[email protected]>
Signed-off-by: Pankaj Patil <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
Signed-off-by: Sibi Sankar <[email protected]>

Add support for SYSTEM_RESET2 vendor-specific resets in
qcs615-ride as reboot-modes.  Describe the resets:
"bootloader" will cause device to reboot and stop in the
bootloader's fastboot mode.  "edl" will cause device to reboot
into "emergency download mode", which permits loading images via
the Firehose protocol.

Link: https://lore.kernel.org/r/20250922-arm-psci-system_reset2-vendor-reboots-v15-14-7ce3a08878f1@oss.qualcomm.com
Signed-off-by: Song Xue <[email protected]>
Signed-off-by: Shivendra Pratap <[email protected]>

QUP devices are currently marked with opp-shared in their OPP table,
causing the kernel to treat them as part of a shared OPP domain. This
leads to the qcom_geni_serial driver failing to probe with error
-EBUSY (-16).

Remove the opp-shared property to ensure the OPP framework treats the
QUP OPP table as device-specific, allowing the serial driver to probe
successfully

Link: https://lore.kernel.org/all/[email protected]/
Fixes: f6746dc ("arm64: dts: qcom: qcs615: Add QUPv3 configuration")
Signed-off-by: Viken Dadhaniya <[email protected]>

Introduce DisplayPort controller node and associated QMP USB3-DP PHY
for SM6150 SoC. Add data-lanes property to the DP endpoint and update
clock assignments for proper DP integration.

Reviewed-by: Dmitry Baryshkov <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
Signed-off-by: Xiangxu Yin <[email protected]>
Link: https://lore.kernel.org/all/20251104-add-displayport-support-to-qcs615-devicetree-v7-3-e51669170a6f@oss.qualcomm.com/

Add DP connector node and configure MDSS DisplayPort controller for
QCS615 Ride platform. Include PHY supply settings to support DP output.

Reviewed-by: Konrad Dybcio <[email protected]>
Signed-off-by: Xiangxu Yin <[email protected]>
Link: https://lore.kernel.org/all/20251104-add-displayport-support-to-qcs615-devicetree-v7-4-e51669170a6f@oss.qualcomm.com/

…symbol

Switch the halt_check method from BRANCH_HALT to BRANCH_HALT_DELAY for
gcc_ufs_phy_rx_symbol_0_clk, gcc_ufs_phy_rx_symbol_1_clk, and
gcc_ufs_phy_tx_symbol_0_clk. These clocks are externally sourced and do
not require polling for halt status.

Fixes: 161b7c4 ("clk: qcom: Add Global Clock controller (GCC) driver for X1E80100")
Link: https://lore.kernel.org/r/20251119-gcc_ufs_phy_clk_branch_delay-v1-1-292c3e40b8c7@oss.qualcomm.com
Signed-off-by: Taniya Das <[email protected]>

Add clock ops for Rivian ELU PLL, add the register offsets for supporting
the PLL.

Reviewed-by: Konrad Dybcio <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Taniya Das <[email protected]>

…M8750 SoC

Add device tree bindings for the camera clock controller on
Qualcomm SM8750 platform. The camera clock controller is split between
camcc and cambist. The cambist controls the mclks of the camera clock
controller.

Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Taniya Das <[email protected]>

…8750 SoC

Add support for the Camera Clock Controller (CAMCC) on the SM8750
platform.

The CAMCC block on SM8750 includes both the primary camera clock
controller and the Camera BIST clock controller, which provides the
functional MCLK required for camera operations.

Reviewed-by: Dmitry Baryshkov <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Taniya Das <[email protected]>

The current RPMh VRM clock definitions do not accurately represent the
hardware mapping of these clocks. While there is no functional impact,
this update aligns the definitions with the hardware convention by adding
the appropriate suffix to indicate the clock divider and the E0 variant
for the C3A_E0, C4A_E0, C5A_E0, and C8A_E0 resources on Glymur.

Reviewed-by: Konrad Dybcio <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Taniya Das <[email protected]>

Add the RPMH clocks present in Kaanapali SoC.

Reviewed-by: Konrad Dybcio <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Taniya Das <[email protected]>

# Conflicts:
#	arch/arm64/boot/dts/qcom/Makefile
#	arch/arm64/boot/dts/qcom/talos.dtsi

# Conflicts:
#	include/linux/firmware/qcom/qcom_scm.h

Adding merge log file and topic_SHA1 file

Signed-off-by: Salendarsingh Gaud <[email protected]>

….org/pub/scm/linux/kernel/git/torvalds/linux.git

tech/bsp/clk 567d776 19
tech/security/firmware-smc a50984a 2
tech/bsp/soc-infra 2949741 9
tech/bsp/remoteproc 27311a4 15
tech/bus/peripherals 486bcf7 1
tech/bus/pci/all 2fdd372 9
tech/bus/usb/dwc 49ac8e0 2
tech/bus/usb/phy cb24d23 11
tech/debug/hwtracing 88c50d8 27
tech/pmic/misc 91e88b9 16
tech/pmic/regulator 81fc8fb 6
tech/mem/iommu fc1b59c 1
tech/mm/audio/all 3a0c2db 4
tech/mm/camss d1d2c38 3
tech/mm/drm 9bb86be 28
tech/mm/fastrpc 844e24f 4
tech/mm/video b5deb4a 15
tech/mm/gpu 1651b6d 5
tech/mproc/rpmsg c3875d9 1
tech/net/ath 2b189c5 19
tech/net/eth c280d7e 1
tech/net/bluetooth b5902f2 2
tech/pm/power 7b7e779 7
tech/pm/thermal 363f414 3
tech/security/crypto fa6b06a 11
tech/storage/all ba8c93d 6
tech/all/dt/qcs6490 87b5b8c 7
tech/all/dt/qcs9100 d8bc255 14
tech/all/dt/qcs8300 f5c9375 27
tech/all/dt/qcs615 5461220 10
tech/all/dt/hamoa 4c89453 11
tech/all/dt/glymur 6e186f9 20
tech/all/dt/kaanapali 9508158 5
tech/all/dt/pakala 6ac5fb5 3
tech/all/config bccaf34 33
tech/overlay/dt 0372190 10
tech/all/workaround 960a7bd 2
tech/mproc/all d19a4c1 5

Disabling sync_state temporarily, until all the client changes get
merged.

Signed-off-by: Raviteja Laggyshetty <[email protected]>